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1b CY 7C1 85
FOR REVIEW ONLY
fax id: 1013
CY7C185
8K x 8 Static RAM
Features
* High speed -- 15 ns * Fast tDOE * Low active power -- 715 mW * Low standby power -- 220 mW * CMOS for optimum speed/power * Easy memory expansion with CE1, CE2 and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP and SOJ package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ Top View
NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 C185-2
I/O0 INPUT BUFFER I/O1 I/O2 I/O3 256 x 32 x 8 ARRA Y I/O4 I/O5 I/O6
CE1 CE2 WE OE C185-1
A1 A2 A3 A4 A5 A6 A7 A8
COLUMN DECODER
POWER DOWN
I/O7
Selection
Guide[1]
7C185-12 12 140 40/15 7C185-15 15 130 40/15 7C185-20 20 110 20/15 7C185-25 25 100 20/15 7C185-35 35 100 20/15
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Shaded areas contain preliminary information. Note: 1. For military specifications, see the CY7C185A/CY7C186A datasheet.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 May 1986 - Revised April 1996
FOR REVIEW ONLY
CY7C185
Pin Configurations (continued)
TSOP Top View OE A1 A2 A3 CE2 WE VCC NC A4 A5 A6 A7 A8 A9
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A12 A11 A10
C185-3
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ............................................ -0.5V to +7.0V DC Input Voltage[2]......................................... -0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
7C185-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 VIH or CE2 VIL Min. Duty Cycle=100% Max. VCC, CE1 VCC - 0.3V, or CE2 0.3V VIN VCC - 0.3V or VIN 0.3V 40 15 Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic Power-Down Current Automatic Power-Down Current Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -5 -5 Min. 2.4 0.4 VCC 0.8 +5 +5 -300 140 40 15 2.2 -0.5 -5 -5 Max. 7C185-15 Min. 2.4 0.4 VCC 0.8 +5 +5 -300 130 mA mA Max. Unit V V V V A A mA mA
Shaded areas contain preliminary information. Notes: 2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns. 3. -Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
FOR REVIEW ONLY
CY7C185
Electrical Characteristics Over the Operating Range (continued)
7C185-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic Power-Down Current Automatic Power-Down Current
[2]
7C185-25, 35 Min. 2.4 Max. 0.4 2.2 -0.5 -5 -5 VCC 0.8 +5 +5 -300 100 20 15 Unit V V V V A A mA mA mA mA
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
2.2 -0.5 GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 VIH or CE2 VIL Min. Duty Cycle=100% Max. VCC, CE1 VCC - 0.3V or CE2 0.3V VIN VCC - 0.3V or VIN 0.3V -5 -5
VCC 0.8 +5 +5 -300 110 20 15
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF
Note: 4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 481 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R1 481 ALL INPUT PULSES 3.0V R2 255
C185-4
R2 255
GND
10%
90%
90% 10% 5 ns
C185-5
5 ns
(a)
(b)
Equivalent to:
THEVENIN EQUIVALENT OUTPUT 167 1.73V
3
FOR REVIEW ONLY
CY7C185
Switching Characteristics Over the Operating Range[5]
7C185-12 Parameter READ CYCLE tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6] 3 3 6 0 12 0 15 CE1 LOW to Low Z[7] CE2 HIGH to Low Z CE1 HIGH to High CE2 LOW to High Z Z[6, 7] 2 6 3 3 7 0 20 3 12 12 6 3 7 5 3 8 0 20 12 12 3 15 15 8 3 8 5 3 10 0 20 15 15 5 20 20 9 3 10 5 3 10 20 20 5 25 25 12 3 10 25 25 5 35 35 15 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C185-15 Min. Max. 7C185-20 Min. Max. 7C185-25 Min. Max. 7C185-35 Min. Max. Unit
CE1 LOW to Power-Up CE2 to HIGH to Power-Up CE1 HIGH to Power-Down CE2 LOW to Power-Down Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[6] WE HIGH to Low Z
WRITE CYCLE[8] tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE 12 8 8 9 0 0 8 6 0 6 3 3 15 12 12 12 0 0 12 8 0 7 5 20 15 15 15 0 0 15 10 0 7 5 25 20 20 20 0 0 15 10 0 7 5 35 20 20 25 0 0 20 12 0 8 ns ns ns ns ns ns ns ns ns ns ns
Shaded areas contain preliminary information. Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4
FOR REVIEW ONLY
CY7C185
Switching Waveforms
Read Cycle No.1[9,10]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C185-6
Read Cycle No.2[11,12]
CE1 tRC
CE2 OE OE
tACE
DATA OUT
tDOE tLZOE HIGH IMPEDANCE tLZCE
tHZOE tHZCE DATA VALID tPD ICC HIGH IMPEDANCE
VCC SUPPLY CURRENT
tPU 50%
50% ISB
C185-7
Write CycleNo. 1 (WE Controlled) [10,12]
tWC ADDRESS CE1 tAW CE2 CE WE tSA tSCE2 tPWE tSCEI tHA
OE tSD DATA I/O NOTE 15 tHZOE
C185-8
tHD
DATA IN VALID
5
FOR REVIEW ONLY
CY7C185
Switching Waveforms (continued)
Write Cycle no.2 (CE Controlled)[12,13,15]
tWC ADDRESS CE1 tSA CE2 tAW WE tSD DATA I/O DATA IN VALID tHD
C185-9
tSCE1
tSCE2 tHA
Write Cycle No.3 (WE Controlled, OE LOW)[12,13,14,15]
tWC ADDRESS CE1 CE2 tSCE1 tSCE2 tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA IN VALID tLZWE
C185-10
tHA
tHD
Notes: 9. Device is continuously selected. OE, CE1 = V IL. CE 2 = VIH. 10. WE is HIGH for read cycle. 11. Data I/O is High Z if OE = VIH, CE1 = V IH, WE = V IL or CE2=V IL. 12. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH and WE LOW. CE 1 and WE must be LOW and CE 2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 14. If CE1 goes HIGH or CE 2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals should not be applied.
6
FOR REVIEW ONLY
CY7C185
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 0.6 0.4 0.2 0.0 4.0 4.5 5.0 I SB 5.5 6.0 0.4 0.2 0.0 -55 ISB 25 125 V CC =5.0V V IN=5.0V 60 40 20 0 0.0 1.0 2.0 3.0 4.0 I CC 0.8 1.2 1.0 I CC NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE 120 100 80 VCC =5.0V TA =25C OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 1.4 1.3 1.2 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 6.0 0.8 0.6 -55 1.0 1.6 1.4
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE 140 120 100 80 60 VCC =5.0V 40 20 25 125 0 0.0
OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE
VCC =5.0V TA =25C
AMBIENT TEMPERATURE (C)
1.0 2.0 3.0 OUTPUT VOLTAGE (V)
4.0
TYPICAL POWER-ON CURRENT vs.SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0
TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING 1.25
NORMALIZED I CC vs.CYCLE TIME VCC =5.0V TA =25C VCC =0.5V 1.00
VCC =4.5V TA =25C
0.75
0
200
400
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
7
FOR REVIEW ONLY
CY7C185
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Input/Output High Z High Z Data Out Data In High Z Mode Deselect/Power-Down Deselect/Power-Down Read Write Deselect
Address Designators
Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 X2 Pin Number 2 3 4 5 6 7 8 9 10 21 23 24 25
Ordering Information
Speed (ns) 12 15 Ordering Code CY7C185-12PC CY7C185-12VC CY7C185-15PC CY7C185-15VC CY7C185-15ZC 20 CY7C185-20PC CY7C185-20VC CY7C185-20ZC 25 CY7C185-25PC CY7C185-25VC CY7C185-25ZC 35 CY7C185-35PC CY7C185-35VC CY7C185-35ZC
Shaded areas contain preliminary information.
Package Name P21 V21 P21 V21 Z28 P21 V21 Z28 P21 V21 Z28 P21 V21 Z28
Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package
Operating Range Commercial Commercial
Commercial
Commercial
Commercial
Document #: 38-00037-K
8
FOR REVIEW ONLY
CY7C185
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
28-Lead Molded SOJ V21
9
FOR REVIEW ONLY
CY7C185
Package Diagrams (continued)
28-Lead Thin Small outline Package Z28
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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